DigiCipher 등하시스템의 하드웨어 구현방법에 관한 연구

A study on the hardware implementation of the digicipher equalization system

In this paper, we present the modified CMA (constant modulus algorithm) and LMS (least mean square) algorithms for digiCipher system with reduced hardware cost, in which the pipelined architecture is employed. They yield the performance comparable to that using floating-point operations. We show the effecstiveness of the proposed architecture through the implementation results using VHDL.