전자공학회논문지B (Journal of the Korean Institute of Telematics and Electronics B)
- 제33B권3호
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- Pages.62-68
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- 1996
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- 1016-135X(pISSN)
155.52 Mbps CMOS 데이타 트랜스미터의 설계
Design of a 155.52 Mbps CMOS data transmitter
초록
A CMOS transmitter ASIC for the ATM switching system etc., was designed to transmit 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is genrated using reference 19.44 MHz clock by an analog PLL while parallel to serial data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is
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