Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 33A Issue 7
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- Pages.176-184
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- 1996
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- 1016-135X(pISSN)
The fabrication process and optimum design of RESURF EDMOSFETs for smart power IC applications
Smart power IC용 RESURF EDMOSFETs의 제조공정과 최적설계
Abstract
To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m
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