Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 33A Issue 5
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- Pages.212-221
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- 1996
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- 1016-135X(pISSN)
Low-voltage low-power comparator design techniques
저전압 저전력 비교기 설계기법
Abstract
A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.
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