대칭적 의사결함처리요소 생성 기법에 의한 결함허용 VLSI 어레이의 신뢰도 향상과 실시간 재구성

Reliability improvement and real-tiem reconfiguration of fault tolerant VLSI arrays using symmetrical pseudo faulty processing elements genration technique

In this paper, we propose a symmetrical pseudo faulty processing elements genration technique to improve the overall reliability of arrays with fixed hardware resources on the fault tolerant VLSI arrays based on single-track switches. We have analyzed the reliability of fault tolerant VLSI arrays and designed control logic for real-tiem reconfiguration. Applying this technique to reconfiguration of VLSI 2-D arrays, we have found that the proposed scheme achieves a higher reliability than the previus methods of similar condition. And we have found that the results of reliability analyzed by mathematic computation are very close to simulated ones. Furthermore, the time overhead for reconfiguration is independent of the array size because the control for reconfiguration is distributively executed by each processing elements. And the proposed scheme has an advantage which maintained properties of VLSI arrays by keeping the locality of interconnections as high as possible even after the reconfiguration.