전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제32A권4호
- /
- Pages.85-92
- /
- 1995
- /
- 1016-135X(pISSN)
여러 개의 FPGA 칩을 위한 대규모 회로의 분할
Partitioning of large-circuits for multiple FPGAs
초록
A new partitioning algorithm has been developed to implement a large circuit by using multiple field programmable gate array (FPGA) chips. While the conventional partitioning is to minimze the number of nets cut under size constraints, partitioning for multiple FPGAs has several additional constraints so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two steps whhich are the intial partitioning for global optimization and the iterative partitioning improvements for constraint satisfaction. Experismental results using the MCNC benchmark examples show that our partition method produces better results thatn those of other recent approaches on the average.
키워드