Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 32A Issue 1
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- Pages.234-243
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- 1995
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- 1016-135X(pISSN)
A VLSI array implementation of vector-radix 2-D fast DCT
Vector-radix 2차원 고속 DCT의 VLSI 어레이 구현
Abstract
An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8
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