전자공학회논문지B (Journal of the Korean Institute of Telematics and Electronics B)
- 제32B권5호
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- Pages.730-736
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- 1995
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- 1016-135X(pISSN)
병렬전류감산기를 이용한 슬루율 가변 연산증폭기 설계
Design of a CMOS Programmable Slew Rate Operational Amplifier with a Switched Parallel Current Subtraction Circuit
초록
This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/
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