A Hardware Scheme to Reduce the Branch Penalty in Pipelined RISC Processors

파이프라인 RISC 프로세서에서 분기지연을 감소시키는 하드웨어 구조

Conditional branch instructions are a major obstacle to the increasing of RISC processor performance, because they can break the smooth flow of instructions; the issuing of instructions after a branch instruction must often wait until the condition is resolved. This paper proposes a hardware scheme which has a duplicated fetching logic to reduce the penalty imposed by conditional branch instructions. The proposed shceme has a buffer to maintain states of processor, which supports the precise interrupt. We make use of two code segments to test the performance and their results were compared with those of the delayed branch. We got the result that the proposed scheme reduces the branch penalty extremely.