전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제32A권5호
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- Pages.749-758
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- 1995
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- 1016-135X(pISSN)
디지탈 신호처리 프로세서의 테스터블 디자인 기법
Testable Design Technique for Digital Signal Processor
초록
There are many testable design techniques, among which Scan path and BIST techniques are mainly used. In this paper, the increase of design effectiveness is discussed, when these techniques are applied to the practical implementation of chips. The following techniques are presented : 1) Blocks are commonly used to reduce test time without hardware increase, 2) MUX is used to implement the shortest Scan path, 3) Scan register is used which controls and/or observes several blocks to avoid the increase of hardware.
키워드