전자공학회논문지B (Journal of the Korean Institute of Telematics and Electronics B)
- 제31B권9호
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- Pages.76-84
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- 1994
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- 1016-135X(pISSN)
완전탐색 블럭정합 알고리듬을 이용한 움직임 추정기의 VLSI 설계 및 구현
Design and Implementation of Motion Estimation VLSI Processor using Block Matching Algorithm
초록
This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.
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