비선형 시냅스를 갖는 확장 가능한 Analog Neuro-chip의 설계

Design of Expandable Neuro-Chip with Nonlinear Synapses

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.