Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 31A Issue 4
- /
- Pages.106-115
- /
- 1994
- /
- 1016-135X(pISSN)
Design of a Time Optimaized Technology Mapping System
타이밍 최적화 기술 매핑 시스템의 설계
Abstract
This paper presents the design of a technology mapping system for optimizing delays of combinational and synchronous sequential logic circuits. The proposed system performs delay optimization for combinational logic circuits by remapping, buffering, and gate merging methods through the correct delay calculation in which the loading values are considered. To get time optimized synchronous sequential circuits, heuristic algorithms are proposed. The proposed algorithms reallocate registers by considering the critical path characteristics. Experimental results show that the proposed system produces a more optimized technology mapping for MCNC benchmarks compared with mis-II.
Keywords