References
- IEEE Trans. on Computer v.C-30 no.10 Performance of processor-memory in-terconnections for multiprocessors Patel, J.H.
- IEEE Trans. on Computer v.C-26 no.5 The indirect binary n-cube microprocessor array Pease, M.C.
- IEEE Trans. on Computer v.C-24 no.12 Access and alignment of data in an array processor Lawrie, D.H.
- Proc. Int'l Conf. Parallel Processing Performance analysis of a redundant path interconnection networks Varma, A.;Raghavendra, C.S.
- IEEE Trans. on Computer v.37 no.5 The Kappa network with fault-tolerant destination tag algorithm Kothari, S.C.;Prabhu, G.M.;Roberts, R.
- Journal of Parallel and Distributed Computing v.5 no.2 Multipath network with cross link Kothari, S.C.;Prabhu, G.M.;Roberts, R.
- IEEE Trans. on Computer v.C-30 no.4 Analysis and simulation of buffered Delta networks Dias, D.M.;Jump, J.R.
- Proc. Int'l Conf. Parallel Processing Performance study of multiple-packet multistage cube networks and comparison to circuit switching Davis, N.J. IV;Siegel, H.J.
- IEEE Trans. on Computer v.39 no.3 Performance analysis of multibuffered packet-wwitching networks in multiprocessor systems Yoon, H.;Lee, Y.;Liu, M.T.
- 9-th Int'l Symp. Computer Architecture The Gamma network: a multiprocessor interconnection net-work with redundant paths Parker, D.S.;Raghavendra, C.S.
- Telecommunication Networks: Protocols Schwartz, M.
- Design of multipath multistage interconnection networks and performance study of multiple-packet switching networks Kim, J.
- IEEE Computer v.14 no.12 Packet switching interconnection networks for modular systems Dias, D.M.;Jump, J.R.
- IEEE Trans. on Computer v.32 no.12 The Performance of multistage interconnection networks for multiprocessors Kruskal, C.P.;Snir, M.
- Computer v.14 no.12 The multistage cube: a versatile interconnection network Siegel, H.J.;McMillen, R.J.