전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제30A권11호
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- Pages.132-139
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- 1993
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- 1016-135X(pISSN)
다단 논리합성을 위한 성능 구동형 회로 다단기
Performance-Driven Multi-Levelizer for Multilevel Logic Synthesis
초록
This paper presents a new performance-driven multi-levelizer which transforms a two-level description into a boolean network of the multilevel structure satisfied with user's costraints, such as chip area, the number of wires and literals, maximum delay, function level, fanin, fanout, etc.. The performance of circuits is estimated by reference to the informations in cell library through the cell mapping phase, and multi-levelization of circuits is constructed by the decomposition using the kernel and factoring concepts. Here, the saving cost of a common subexpression is defined to the sum of area and delay saved, when it is substituted. The experiments with MCNC benchmarks show the efficiency of the proposed method.
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