전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제30A권10호
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- Pages.67-76
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- 1993
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- 1016-135X(pISSN)
다층 레벨 VHDL 시뮬레이터의 설계
Design of a Multi-level VHDL Simulator
초록
This paper presents the design and implementation of SVSIM (Sogang VHDL SIMulator), a multi-level VHDL simulator, designed for the construction of an integrated VGDL design environment. The internal model of SVSIM is the hierarchical C/DFG which is extended from C/DFG to include the network hierarchy and local/glabal control informations. Hierarchical network is not flattened for simulation, resulting in the reduction of space complexity. The predufined/user-defined types except for the record type and the predefined/user-defined attributes are supported in SVSIM. Algorithmic-level descriptions can be siumlated by the support of recursive procedure/function calls. Input stimuli can be generated by command script in stimuli file or in VHDL source code. Experimential results show SVSIM can be efficiently used for the simulation of the pure behavioral descriptions, structural descriptions or mixture of these.
키워드