Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 30A Issue 5
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- Pages.52-62
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- 1993
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- 1016-135X(pISSN)
Implementation of a Layout Generation System for the Gate Matrix Style
Gate Matrix 레이아웃 생성 시스템의 구현
Abstract
This paper describes the implementation of a layout generation system for the gate matrix style to implement multi-level logic. To achieve improved layouts from general net lists, the proposed system performs flexible net binding for series nets. Also the system reassings gates by the heuristic information that shorter net lengths are better for the track minimization. By track minimizing with subdividing layout column information, the system decreases the number of necessary layout tracks. Experimental results show that the system generates more area-reduced (approximately 7.46%) layouts than those by previous gate matrix generation systems using net list inputs.
Keywords