Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 29A Issue 4
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- Pages.91-98
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- 1992
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- 1016-135X(pISSN)
A New Design Method for Verification Testability
검증 테스팅을 위한 새로운 설계 방법
Abstract
In this paper, a new heuristic algorithm for designing combinational circuits suitable for verification testing is presented. The design method consists of argument reduction, input partitioning, output partitioning, and logic minimization. A new heuristic algorithm for input partitioning and output partitioning is developed and applied to designing combinational circuits to demonstrate its effectiveness.
Keywords