A Study on The design of Accelerator of The Outlined Font Generation

고해상도 윤곽선 문자 발생가속기 설계에 대한 연구

This paper presents a design of the accelerate circuit for the conversion of the vector font data into the bit-mapped image. Among the Bezier curve algorithm, the subdivision algorithm gives the good performance and easy hardware implementation. The sequencer is realized by the proprammable gate array and the processing unit is composed of EPLDs and TTL ICs.