조합회로에 대한 계층 구조적 테스트 패턴 생성 알고리즘의 비용 모델

A Cost Model of Hierarchical Automatic Test Pattern Generation Algorithms for Combinational Logic Circuits

A cost model of test generation is presented in this paper. The cost of flat gate-level and hierarchical modular level test generation for combinational logic circuits are modeled. The model shows that the cost of hierarchical test generation grows as GlogGunder some assuptions, while the cost of gate-level test generation grows $G^2<$/TEX>, where G is the number of gates in a circuit under test. The cost model derived in this paper is used to explain why some test generation techniques are faster and why hierarchical test generators should be faster than flat test generators on large circuits.