전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제28A권5호
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- Pages.387-397
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- 1991
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- 1016-135X(pISSN)
Fanout 제약 조건하의 논리 회로 합성
Fanout Constrained Logic Synthesis
초록
This paper presents the design and implementation of a performance-driven logic synthesis system that automatically generates circuits satisfying the given timing and fanout constraints in minimal silicon area. After performing technology independent and dependent optimization, the system identifies and resynthesizes the gates with large loading delay due to excessive fanouts to eliminate the critical path. Experimental results for MCNC benchmark circuits show that proposed system generates the circuits with less delay by up to 20%.
키워드