Logic-Level Design of the Application Specific IC for the Processing of Binary Images in the Hierarchical Representation

구조적 표현의 이진 화상 처리를 위한 ASIC의 논리 레벨 설계에 관한 연구

The purpose of this study is to process binary images of Breadth First Linear Quadtree in hardware. Inthis paper, we designed and verified logic level circuit of ASIC for the encoding part of the binary image that is to convert the binary image into the representation of the Breadth First Linear Quadtree. The logic level circuit is composed of cells in TTL library. The significance of thes study is to implement an algorithm by hardware rather than by software, so that the processing time can be reduced by about 20 times.