The Transactions of the Korean Institute of Electrical Engineers (대한전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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Logic-Level Design of the Application Specific IC for the Processing of Binary Images in the Hierarchical Representation

구조적 표현의 이진 화상 처리를 위한 ASIC의 논리 레벨 설계에 관한 연구

  • 김종완 (서울대 대학원 컴퓨터공학과) ;
  • 최희창 (서울대 대학원 컴퓨터공학과) ;
  • 최정훈 (서울대 대학원 컴퓨터공학과) ;
  • 김승기 (서울대 대학원 컴퓨터공학과) ;
  • 이기한 (서울대 대학원 컴퓨터공학과) ;
  • 김경식 (ETRI 사무설계기기연구실) ;
  • 황희영 (서울대 공대 컴퓨터공학과)
  • Published : 1990.07.01
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Abstract

The purpose of this study is to process binary images of Breadth First Linear Quadtree in hardware. Inthis paper, we designed and verified logic level circuit of ASIC for the encoding part of the binary image that is to convert the binary image into the representation of the Breadth First Linear Quadtree. The logic level circuit is composed of cells in TTL library. The significance of thes study is to implement an algorithm by hardware rather than by software, so that the processing time can be reduced by about 20 times.

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