Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)
- Volume 25 Issue 8
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- Pages.998-1009
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- 1988
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- 1016-135X(pISSN)
Hierarchical Circuit Extract Algorithm for VLSI Design Verification
VLSI의 설계검증을 위한 계층적 회로 추출 알고리듬
Abstract
A Hierarchical Circuit Extract Algotithm, which efficiently extract circuits from VLSI mask pattern information, is programmed. Quad-tree is used as a data structure which includes various CIF circuit elements and instances. This system is composed of CIF input routine, Quad-tree making routine, Transistor finding routine and Connection list making routine. This circuit extractor can extract circuit with hierarchical structure of circuit. This system is designed using YACC and LEX. By programming this algorithm with C language and adopting to various circuits, the effectiveness of this algorithm is showed.
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