A Design of Pipelined Memory Access Control for Multiprocessor Systems and its Evaluation

다중프로세서시스테멩 대한 파이프라인 방식 메모리 접근제어의 설계와 그 효율분석

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.