A Pipelined Architecture for Maze Routing

  • Won Young Ju (Korea Military Academy) ;
  • Sahni Sartaj K. (University of Minnesota)
  • Published : 1987.12.01

Abstract

This paper presents a hardware accelerator for the maze routing problem. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.

Keywords