The Transactions of the Korean Institute of Electrical Engineers (대한전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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The Three-Level PLA Design Using EXANOR

Mn-Zm-Fe Ferrite에서 하소 및 소결조건이 투자율과손실에 미치는 영향

  • 조동섭 (서울대 대학원 전자계산기공학과) ;
  • 이종원 (서울대 대학원 전자계산기공학과) ;
  • 황희영 (서울대 공대 전자계산기공학과)
  • Published : 1983.01.01
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Abstract

This paper deals with the three-level PLA constructed by EXCLUSIVE-OR, AND, and OR. (abbreviated as EXANOR). Most PLA circuits have constraints on minimum chip area and minimal input lines. Thus, the reduction of PLA chip area is an important factor in design of logic circuits. In this paper, newly constructed architecture of PLA is proposed and then, its reduction effect is proved theoretically and some of selected examples are illustrated for designing three-level PLA circuits.

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