전력전자학회:학술대회논문집 (Proceedings of the KIPE Conference)
- 전력전자학회 2017년도 추계학술대회
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- Pages.7-8
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- 2017
비정현 계통 전압하에서 단상 인버터의 PLL 성능 개선 방법
A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions
- Khan, Reyyan Ahmad (Department of Electrical Engineering, Soongsil University) ;
- Ashraf, Muhammad Noman (Department of Electrical Engineering, Soongsil University) ;
- Choi, Woojin (Department of Electrical Engineering, Soongsil University)
- 발행 : 2017.11.24
초록
The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.
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