EDISON SW 활용 경진대회 논문집 (Proceeding of EDISON Challenge)
- 제2회(2013년)
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- Pages.266-268
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- 2013
Analyze the channel doping concentration characteristics of junctionless nanowire transistors by using Edison simulation
- Choi, Jun Hee (Korea University, Electrical engineering) ;
- Lee, Byung Chul (Korea University, Electrical engineering) ;
- Kim, Jung Do (Korea University, Electrical engineering)
- 발행 : 2013.04.17
초록
In this paper, we study the channel doping concentration characteristics of junctionless nanowire transistors (JLT) using Edison nanowire FET device simulation. JLT has no junctions by very simple fabrication process. And this device has less variability and better electrical properties than classical inversion-mode transistors with PN junctions at the source and drain. In this simulation we use tri-gate structure. Source and drain doping concentration is
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