Power Consumption Analysis for Security attack in TPM

Recently, most network communication chips are powered; which causes power consumption a heavily constraint. Since, there are a lot of expectations on TPM to have a high performance in terms of authentication of its device. During the design process there is a need to estimate the security of the design but it always when the chip has already been manufactured. This paper designed a power consumption control monitor in TPM device which evaluate the voltage drop during processing of use. Therefore we will analyze the power consumption profile. The result shows that the voltage drop leads to vulnerability of the system to attackers during communication process.