한국정보통신학회:학술대회논문집 (Proceedings of the Korean Institute of Information and Commucation Sciences Conference)
- 한국해양정보통신학회 2011년도 추계학술대회
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- Pages.398-401
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- 2011
고효율 CMOS PWM DC-DC 벅 컨버터
High-Efficiency CMOS PWM DC-DC Buck Converter
- Kim, Seung-Moon (University of Incheon) ;
- Son, Sang-Jun (University of Incheon) ;
- Hwang, In-Ho (University of Incheon) ;
- Yu, Sung-Mok (University of Incheon) ;
- Yu, Chong-Gun (University of Incheon)
- 발행 : 2011.10.26
초록
본 논문에서는 고효율의 CMOS PWM DC-DC 벅 변환기를 설계하였다. 설계된 CMOS PWM DC-DC 벅 변환기는 입력전압(3.4-3.9V)로부터 일정한 출력전압(1-2.8V)을 생성한다. Inductor-based 방식을 택하였고, 제어 대상은 전류이며, Pulse Width Modulation(PWM) 모드로 동작한다. 회로 구성은 Power Switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator, Modulator 등 이다. 제안된 CMOS PWM DC-DC 벅 컨버터는 Switching Frequency가 약 1MHz이고, 부하 전류가 약 40mA이상부터 CCM동작을 하며 100mA일 때 98.71%의 최대 효율을 갖는다. 또한, 출력전압 리플은 0.98mV이다(입력전압 3.5V, 출력전압 2.5V 기준). 제안된 회로의 검증을 위해 CMOS
This paper presents a high-efficiency CMOS PWM DC-DC buck converter. It generates a constant output voltage(1-2.8V), from an input voltage(3.4-3.9V). Inductor-based type is chosen and inductor current is controlled with PWM operation. The designed circuit consists of power switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator and Modulator. Switching Frequency is 1MHz, It operates in CCM when the load current is more than 40mA, and the maximum efficiency is 98.71% at 100mA. Output voltage ripple is 0.98mV(input voltage:3.5V, output voltage:2.5V). The performance of the designed circuit has been verified through extensive simulation using a CMOS