A study on the key Issues for implementing the IEC61850 based Gateway

IEC61850 기반의 Gateway 개발을 위한 이슈에 관한 연구

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.