대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

ODC 클럭 게이팅을 이용한 저전력 Interface 회로설계

Design of Low- Power Interface using Clock Gating Based on ODC Computation

  • 양현미 (청주대학교 전자 정보통신공학부) ;
  • 김희석 (청주대학교 전자 정보통신공학부)
  • Yang, Hyun-Mi (School of Information and Electronic Engineering Chong Ju University) ;
  • Kim, Hi-Seok (School of Information and Electronic Engineering Chong Ju University)
  • 발행 : 2008.06.18
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초록

In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

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