대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2008년도 하계종합학술대회
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- Pages.399-400
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- 2008
연산 공유 및 효율적인 스케줄링에 기반을 둔 H.264 디코더용 통합 IP/IT/IQ/MC 회로 구조
Architecture of Unified IP/IT/IQ/MC Circuit for H.264 Decoder Based on Operation Sharing and Efficient Scheduling
- Chun, Dong-Yeob (Department of Electronics and Information Engineering Hankuk University of Foreign Studies) ;
- Lee, Seon-Young (Department of Electronics and Information Engineering Hankuk University of Foreign Studies) ;
- Cho, Kyeong-Soon (Department of Electronics and Information Engineering Hankuk University of Foreign Studies)
- 발행 : 2008.06.18
초록
This paper presents a new architecture of unified IP/IT/IQ/MC circuit for H.264 decoder based on operation sharing and efficient scheduling. The resultant circuit based on the proposed architecture uses only 12 adders and 1 multiplier. We further reduced the circuit size by sharing buffers. Our circuit consists of 47,810 gates and operates at the maximum operating frequency of 117MHz with 130nm standard cells.
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