대한기계학회:학술대회논문집 (Proceedings of the KSME Conference)
- 대한기계학회 2008년도 추계학술대회A
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- Pages.1289-1294
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- 2008
효율적인 ESD(ElectroStatic Discharge) test를 위한 Stress mode 제안
Stress mode proposal for an efficient ESD test
- 발행 : 2008.11.05
초록
Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.
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