대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 2008년도 제39회 하계학술대회
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- Pages.2275-2276
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- 2008
EISC processor의 속도 향상을 위한 pipelineing 최적화
EISC pipelineing optimizations for processor speed improvements
- Son, Mu-Chang (School of Information&Communication Engineering, Sungkyunkwan University) ;
- Kim, In-Soo (School of Information&Communication Engineering, Sungkyunkwan University) ;
- Min, Hyoung-Bok (School of Information&Communication Engineering, Sungkyunkwan University) ;
- Lee, Young-Geol (Division of Computer Science and Information, Daelim College)
- 발행 : 2008.07.16
초록
Currently the quarter prediction giga it is used SE3208 from EISC ISA [1]] where it does in base. But the prediction which is perfect is difficult improved Pipeline structures and PC the structure which is not Delay to add it decided. Even PC and IF/ID blocks, the area and expense were added, but Bubble without it will be able to control Conditional Branch doors and the possibility of decreasing a help in processor performance improvements.
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