Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Efficient ACS Design for High Speed Viterbi Decoder

고속 비터비 디코더를 위한 효율적인 ACS 설계

  • Lee, Seul-Ki (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Kim, In-Soo (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Min, Hyoung-Bok (School of Information&Communication Engineering, Sungkyunkwan University) ;
  • Ryu, Joong-Kyung (Division of Computer Science and Information, Daelim College)
  • 이슬기 (성균관대학교 정보통신공학부) ;
  • 김인수 (성균관대학교 정보통신공학부) ;
  • 민형복 (성균관대학교 정보통신공학부) ;
  • 류중경 (대림대학 컴퓨터정보계열)
  • Published : 2008.07.16
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Abstract

It respects the high speed of the Bitter expense decoder from the present paper ACS (Add Compare Select) block structures of new method it proposed. It became component anger of existing and it substituted it added all input price it predicted with the method which reduces the operation which is unnecessary it chose respectively ACS unit and a union logical operation circuit and the result after operation one in advance.

Keywords