대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2006년도 하계종합학술대회
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- Pages.521-522
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- 2006
SIMULINK를 이용한 Fractional-N 주파수합성기의 모델링 기법
A SIMULINK Modeling for a Fractional-N Frequency Synthesizer
- 김인정 (국민대학교 전자정보통신대학 전자공학부) ;
- 서우형 (국민대학교 전자정보통신대학 전자공학부) ;
- 안진오 (국민대학교 전자정보통신대학 전자공학부) ;
- 김대정 (국민대학교 전자정보통신대학 전자공학부)
- Kim, In-Jeong (Integrated Circuit Design Lab School of Electronical Engineering, Kookmin University) ;
- Seo, Woo-Hyong (Integrated Circuit Design Lab School of Electronical Engineering, Kookmin University) ;
- Ahn, Jin-Oh (Integrated Circuit Design Lab School of Electronical Engineering, Kookmin University) ;
- Kim, Dae-Jeong (Integrated Circuit Design Lab School of Electronical Engineering, Kookmin University)
- 발행 : 2006.06.21
초록
This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. The SIMULINK modeling was built in the frequency-time mixed domain whereas the Verilog-a modeling was built purely in the time domain. The simulated results of the two models were verified to show the same performance within the error tolerance. This top-down design method can provide the readiness for the transistor-level design.
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