Design of Ultra Low Power Processor for Ubiquitous Sensor Node

유비쿼터스 센서 노드를 위한 저전력 프로세서의 개발

  • 신치훈 (과학기술연합대학교 컴퓨터 및 소프트웨어 공학과) ;
  • 오명훈 (한국전자통신연구원 서버플랫폼연구팀) ;
  • 박경 (한국전자통신연구원 서버플랫폼연구팀) ;
  • 김성운 (한국전자통신연구원 서버플랫폼연구팀)
  • Published : 2006.04.29

Abstract

In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 KHz (0.3 MIPS) while consuming only about few pJ/instruction.

Keywords