대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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- Pages.142-144
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- 2006
전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현
Implementation of Ternary Adder and Multiplier Using Current-Mode CMOS
초록
In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under
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