대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

CMOS 공정을 이용한 Cascode 구조의 LNA 설계

The Study on Design of the CMOS Cascode LNA

  • 오재욱 (중앙대학교 전자전기공학부) ;
  • 하상훈 (중앙대학교 전자전기공학부) ;
  • 김형석 (중앙대학교 전자전기공학부)
  • Oh, Jae-Wook (School of Electronic and Electrical Engineering, Chung-Ang University) ;
  • Ha, Sang-Hoon (School of Electronic and Electrical Engineering, Chung-Ang University) ;
  • Kim, Hyeong-Seok (School of Electronic and Electrical Engineering, Chung-Ang University)
  • 발행 : 2006.07.12
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초록

A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.

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