Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2006.07c
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- Pages.1601-1602
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- 2006
The Study on Design of the CMOS Cascode LNA
CMOS 공정을 이용한 Cascode 구조의 LNA 설계
- Oh, Jae-Wook (School of Electronic and Electrical Engineering, Chung-Ang University) ;
- Ha, Sang-Hoon (School of Electronic and Electrical Engineering, Chung-Ang University) ;
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Kim, Hyeong-Seok
(School of Electronic and Electrical Engineering, Chung-Ang University)
- Published : 2006.07.12
Abstract
A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.
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