Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2005.11a
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- Pages.865-868
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- 2005
A Low Power UART Design by Using Clock-gating
클록 게이팅을 이용한 저전력 UART 설계
- Oh, Tae-Young (Department of Electronic Engineering, Chongju University) ;
- Song, Sung-Wan (Department of Electronic Engineering, Chongju University) ;
- Kim, Hi-Seok (Department of Electronic Engineering, Chongju University)
- Published : 2005.11.26
Abstract
This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess
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