Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2005.10b
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- Pages.309-311
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- 2005
Design of Reconfigurable Hardware for FIR Filters
재구성 가능한 FIR 필터 하드웨어 구조 설계
Abstract
In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.