Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Development of process technique of the alumina membrane with nano-sized pore array

나노미터 크기의 미세구조물을 제작하기 위한 공정기술 개발

  • Lee, J.H. (Division of Information Technology Engineering, Soonchenhyang University) ;
  • Lee, B.W. (Division of Information Technology Engineering, Soonchenhyang University) ;
  • Kim, C.K. (Division of Information Technology Engineering, Soonchenhyang University) ;
  • Lee, K.H. (Department of materials Engineering, Soonchenhyang University)
  • 이재홍 (순천향대학교 정보기술공학부) ;
  • 이병욱 (순천향대학교 정보기술공학부) ;
  • 김창교 (순천향대학교 정보기술공학부) ;
  • 이경호 (순천향대학교 신소재공학과)
  • Published : 2005.07.18
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Abstract

We fabricated an alumina membrane with nano-sized pore array by anodic oxidation using the thin film aluminum deposited on silicon wafer. It is important that the sample prepared by metal deposition method has a flat aluminum surface and a good adhesion between the silicon wafer and the thin film aluminum. The oxidation time was controlled by observation of current variation. The nano-sized pores with diameter of $60{\sim}120nm$ was obtained by $40{\sim}80$ voltage. The pore widening process was employed for obtaining the flat surface because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of rough surface. Finally, the sample was immersed to the phosphoric acid with 0.1M concentration to etching the barrier layer. The sample will be applied to electronic sensors, field emission display, and template for nano- structure.

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