대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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- Pages.70-73
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- 2004
A Study on Place and Route for FPGA using the Time Driven Optimization
- Yi Myoung Hee (Korea Power Exchange) ;
- Yi Jae Young (Technical Univ.) ;
- Tsukiyama Shuji (Chuo University) ;
- Laszlo Szirmay (Technical Univ.)
- 발행 : 2004.08.01
초록
We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.