대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 2004년도 심포지엄 논문집 정보 및 제어부문
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- Pages.153-155
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- 2004
Memory Tester용 ASIC 칩의 설계
The Design of ASIC chip for Memory Tester
- 발행 : 2004.05.22
초록
In this paper, we design the memory tester chip playing an important role in the memory tester as central parts. Memory tester has the sixteen inner instructions to control the test sequence and the address and data signals to DUT. These instructions are saved in memory with each block such as sequencer and pattern generator. Sequencer controls the test sequence according to instructions saved in the memory. And Pattern generator generates the address and data signals according to instructions saved in the memory, too. We can use these chips for various functional test of memory.
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