대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Timing Window Shifting by Gate Sizing for Crosstalk Avoidance

  • 이형우 (서강대학교 전자계산학과) ;
  • 장나은 (서강대학교 전자계산학과) ;
  • 김주호 (서강대학교 전자계산학과)
  • Lee, Hyung-Woo (CAD & VLSI Lab. Dept. of Computer Science Sogang University) ;
  • Jang, Na-Eun (CAD & VLSI Lab. Dept. of Computer Science Sogang University) ;
  • Kim, Ju-Ho (CAD & VLSI Lab. Dept. of Computer Science Sogang University)
  • 발행 : 2004.06.01
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초록

This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average $8.64\%$ Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.

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