대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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- Pages.581-584
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- 2004
크로스톡 회피를 위한 게이트 사이징을 이용한 타이밍 윈도우 이동
Timing Window Shifting by Gate Sizing for Crosstalk Avoidance
- Lee, Hyung-Woo (CAD & VLSI Lab. Dept. of Computer Science Sogang University) ;
- Jang, Na-Eun (CAD & VLSI Lab. Dept. of Computer Science Sogang University) ;
- Kim, Ju-Ho (CAD & VLSI Lab. Dept. of Computer Science Sogang University)
- 발행 : 2004.06.01
초록
This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average
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