대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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- Pages.455-458
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- 2004
단일화된 게이트 프리징, 사이징 및 버퍼삽입에 의한 저 전력 최적화 알고리즘
Gate Freezing, Gate Sizing, and Buffer Insertion for reducing Glitch Power Dissipation
- Lee, Hyung-Woo (Dept. of Computer Science, Sogang University) ;
- Shin, Hak-Gun (Dept. of Computer Science, Sogang University) ;
- Kim, Ju-Ho (Dept. of Computer Science, Sogang University)
- 발행 : 2004.06.01
초록
We present an efficient heuristic algorithm to reduce glitch power dissipation in combinational circuits. In this paper, the total number of glitches are reduced by replacing existing gates with functionally equivalent ones and by gate sizing which classified into three types and by buffer insertion which classified into two types. The proposed algorithm combines gate freezing, gate sizing. and buffer insertion into a single optimization process to maximize the glitch reduction. Our experimental results show an average of
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