Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2004.06b
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- Pages.435-438
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- 2004
An Effective Power/Ground Network Design of VLSI Circuits to Suppress RLC Resonance Effects
공진현상을 감소시키기 위한 효율적인 파워/그라운드 네트워크 디자인
- Ryu, Soon-Keol (Hanyang University, Dept. of Electrical and Computer Engineering) ;
- Eo, Yung-Seon (Hanyang University, Dept. of Electrical and Computer Engineering) ;
- Shim, Jong-In (Hanyang University, Dept. of Electrical and Computer Engineering)
- Published : 2004.06.01
Abstract
This paper presents a new analytical model to suppress RLC resonance effects in power/ground lines due to a decoupling capacitor. First, the resonance frequency of an RLC circuit which is composed of package inductance. decoupling capacitor, and output drivers is accurately estimated. Next, using the estimated resonance frequency, a suitable decoupling capacitor sire is determined. Then, a novel design methodology to suppress the resonance effects is developed. Finally, its validity is shown by using
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